The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and system for using a continuous line-type pattern to form landing polysilicon contacts in integrated circuit devices. Merely by way of example, the invention has been applied to dynamic random access memory devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to a variety of other applications such as application specific integrated circuits, microprocessors, microcontrollers, other memory applications, and the like.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the formation of devices of increasingly small geometries used for the manufacture of integrated circuits in a cost effective and efficient way.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, as device geometry continues to shrink, it becomes increasing difficult to form small contact holes. FIGS. 1a-1c are view diagrams for a conventional contact hole patterning method. As shown, FIG. 1a is a top view of a contact hole layout diagram with lateral contact hole dimension about 130 nm and vertical dimension about 140 to 180 nm. FIG. 1b is a top view of photo resist patterns superimposed over contact hole layout patterns. It can be seem that the contact hole patterns formed in the photoresist are rounded structures with varying sizes. FIG. 1c is a 3-dimensional view diagram of contact hole patterns in the photoresist, showing the circular openings and varying sizes. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.